CVE-2026-90429

CVE-2026-90429

High · published September 17, 2026

CVSS v3.1
7.8
EPSS
0%
Percentile
4.5
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

iommu/tegra241-cmdqv: Synchronize the error ISR against VINTF (de)init

A user VINTF is torn down by tegra241_cmdqv_deinit_vintf(), which runs from

the destroy callback and from the init-failure unwind in the alloc handler.

It clears the cmdqv->vintfs[] slot and lets the iommufd core free it, but

nothing serializes that against the error interrupt: tegra241_cmdqv_isr()

reads cmdqv->vintfs[idx] and dereferences the vintf. A concurrent error can

make the ISR read a slot mid-clear (a NULL deref) or use a vintf which is

about to be freed (a use-after-free).

deinit_vintf() also returns idx to the IDA before clearing the slot, so a

concurrent create that reuses idx can publish its new vintf into the slot,

only for this teardown to erase it again with the stale NULL store.

On the other end, tegra241_cmdqv_init_vintf() publishes a new vintf with a

plain store to the cmdqv->vintfs[] slot, and the ISR dereferences fields of

a published vintf such as vintf->base. A plain store gives no ordering on a

weakly-ordered CPU, and a stale VINTF_ERR_MAP bit on a reused idx can make

the ISR pick a vintf the moment it is published, before its fields are set

or tegra241_vintf_hw_init() runs.

The cmdqv->vintfs[0] slot stays NULL until tegra241_cmdqv_init_structures()

first creates VINTF0, so the slot 0 read needs the same NULL check.

Publish every slot with an smp_store_release(), and read each slot in the

ISR with an smp_load_acquire() under a NULL check, so the ISR always sees

a fully built vintf or NULL. Also make deinit_vintf() clear the slot, and

synchronize_irq() prior to returning idx to the IDA, so no vintf is freed

under a running handler and no reused idx is clobbered.

The record
Technical detail
CVSS v3.1
7.8 · HIGH
Vector
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
CVSS v4.0
Not supplied
EPSS
0.00157 · 4.5th percentile
Published
2026-09-17T21:17Z
References (3)
EPSS history
Timeline
  • 19 SEP 03:55Z
    EPSS moved — → 0%
    epss
  • 17 SEP 16:09Z
    iommu/tegra241-cmdqv: Synchronize the error ISR against VINTF (de)init
    cvelistv5