CVE-2026-90338

CVE-2026-90338

published September 17, 2026

CVSS
—
EPSS
0%
Percentile
10.2
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

serial: amba-pl011: keep console clock enabled for atomic writes

pl011_console_write_atomic() runs from nbcon atomic context, where

sleeping is not allowed. It calls clk_enable(), which takes the common-clk

enable_lock. Under PREEMPT_RT that is a sleeping lock:

clk_enable_lock() first tries spin_trylock_irqsave(), but on contention

falls back to spin_lock_irqsave(). Therefore, an atomic-context printk on

an RT kernel with a clk-backed pl011 can trip:

BUG: sleeping function called from invalid context at spinlock_rt.c:48

__might_resched from rt_spin_lock

rt_spin_lock from clk_enable_lock

clk_enable_lock from clk_enable

clk_enable from pl011_console_write_atomic

... from vprintk_emit

This was found and reproduced on PREEMPT_RT. Arm32 and arm64 DT SoCs are

affected; arm64 SBSA/ACPI has no clk, so clk_enable(NULL) short-circuits

before the lock. In addition, write_atomic() may be invoked from NMI

context and is documented to avoid locking. Removing clk_enable() from

the callback also avoids a potentially unsafe NMI acquisition of the

common-clock enable_lock.

An nbcon atomic-capable console must be printable from any context, so

the clock cannot be gated between writes. Enable the clock while the

console is available for output: use clk_prepare_enable() in

pl011_console_setup(), release it via clk_disable_unprepare() in the

console .exit() callback, and drop the per-write clk_enable()/clk_disable()

pairs from write_atomic() and write_thread().

When printk suspends consoles, drop the reference after

uart_suspend_port() stops console access and restore it before

uart_resume_port() -- but only if suspend actually marked the port

suspended (a wake-capable tty stays running and must keep its clock), and

keep it when console_suspend_enabled is false so no_console_suspend works.

The active power cost of keeping the clock enabled is platform-dependent:

none where the UART clock is a fixed always-on oscillator, real where it

is a gateable clock branch, which then cannot be gated (nor possibly can

its parent clocks) while the console is available for output. When serial

core actually suspends the port, the reference is released so the clock

provider can gate the clock tree.

The record
Technical detail
CVSS
Not scored
CVSS v4.0
Not supplied
EPSS
0.00206 · 10.2th percentile
Published
2026-09-17T21:17Z
References (3)
EPSS history
Timeline
  • 19 SEP 03:55Z
    EPSS moved — → 0%
    epss
  • 17 SEP 16:08Z
    serial: amba-pl011: keep console clock enabled for atomic writes
    cvelistv5