CVE-2026-80727

CVE-2026-80727

published September 3, 2026

CVSS
—
EPSS
0%
Percentile
5.8
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

x86/mce: Set up the polling timer before CMCI discovery

I hit the following on one of my machines:

mce: CPU0 BANK15 CMCI inherited storm

------------[ cut here ]------------

ODEBUG: assert_init not available (active state 0) object: (____ptrval____) object type: timer_list hint: 0x0

WARNING: lib/debugobjects.c:632 at debug_object_assert_init+0x178/0x230, CPU#0: swapper/0/0

CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 7.2.0-rc5 #3 PREEMPTLAZY

RIP: 0010:debug_object_assert_init+0x18f/0x230

Call Trace:

<TASK>

__mod_timer

mce_timer_kick

cmci_discover

intel_init_cmci

mce_intel_feature_init

mcheck_cpu_init

identify_cpu

identify_boot_cpu

arch_cpu_finalize_init

start_kernel

A second splat follows right after, from timer_setup() finding that same

timer already queued:

ODEBUG: init active (active state 0) object: (____ptrval____) object type: timer_list hint: stub_timer+0x0/0x10

This is happening because CMCI storm detection is trying to modify the timer

before latter was properly set up.

Set up the timer first. __mcheck_cpu_setup_timer() only calls timer_setup(),

and depends on neither the generic nor the vendor init.

[ bp: Massage commit message. ]

The record
Technical detail
CVSS
Not scored
CVSS v4.0
Not supplied
EPSS
0.00168 · 5.8th percentile
Published
2026-09-03T17:06Z
References (4)
EPSS history
Timeline
  • 04 SEP 03:44Z
    EPSS moved — → 0%
    epss
  • 03 SEP 08:21Z
    x86/mce: Set up the polling timer before CMCI discovery
    cvelistv5