CVE-2026-74439

CVE-2026-74439

Critical · published August 15, 2026

CVSS v3.1
9.3
EPSS
0%
Percentile
8.8
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry

device_pasid_table_teardown() zeroes the 128-bit scalable-mode context

entry with context_clear_entry() while the Present bit is still set. This

creates a window where the hardware can fetch a torn entry, with some

fields already zeroed while Present is still set, leading to unpredictable

behavior or spurious faults. The context-cache invalidation is issued only

after the entry has been zeroed, and intel_pasid_free_table() then frees

the PASID directory pages, so the IOMMU can keep walking a stale Present=1

entry that points at freed memory.

While x86 provides strong write ordering, the compiler may reorder the two

64-bit writes to the entry, and the hardware fetch is not guaranteed to be

atomic with respect to multiple CPU writes.

Commit c1e4f1dccbe9d ("iommu/vt-d: Clear Present bit before tearing down

context entry") fixed this exact pattern in domain_context_clear_one() and

the copied-context path, but device_pasid_table_teardown() was not

converted.

Align it with the "Guidance to Software for Invalidations" in the VT-d

spec, Section 6.5.3.3, using the same ownership handshake as the sibling

fix: clear only the Present bit, flush it to the IOMMU, perform the

context-cache invalidation, and only then zero the rest of the entry.

The record
Technical detail
CVSS v3.1
9.3 · CRITICAL
Vector
CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:H
CVSS v4.0
Not supplied
EPSS
0.00196 · 8.8th percentile
Published
2026-08-15T10:22Z
References (4)
EPSS history
Timeline
  • 15 AUG 05:59Z
    iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
    cvelistv5