CVE-2026-53056

drm/msm/dpu: fix mismatch between power and frequency

published June 24, 2026

CVSS
—
EPSS
0%
Percentile
5.1
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

drm/msm/dpu: fix mismatch between power and frequency

During DPU runtime suspend, calling dev_pm_opp_set_rate(dev, 0) drops

the MMCX rail to MIN_SVS while the core clock frequency remains at its

original (highest) rate. When runtime resume re-enables the clock, this

may result in a mismatch between the rail voltage and the clock rate.

For example, in the DPU bind path, the sequence could be:

cpu0: dev_sync_state -> rpmhpd_sync_state

cpu1: dpu_kms_hw_init

timeline 0 ------------------------------------------------> t

After rpmhpd_sync_state, the voltage performance is no longer guaranteed

to stay at the highest level. During dpu_kms_hw_init, calling

dev_pm_opp_set_rate(dev, 0) drops the voltage, causing the MMCX rail to

fall to MIN_SVS while the core clock is still at its maximum frequency.

When the power is re-enabled, only the clock is enabled, leading to a

situation where the MMCX rail is at MIN_SVS but the core clock is at its

highest rate. In this state, the rail cannot sustain the clock rate,

which may cause instability or system crash.

Remove the call to dev_pm_opp_set_rate(dev, 0) from dpu_runtime_suspend

to ensure the correct vote is restored when DPU resumes.

Patchwork: https://patchwork.freedesktop.org/patch/710077/

The record
Technical detail
CVSS
Not scored
CVSS v4.0
Not supplied
EPSS
0.00162 · 5.1th percentile
Published
2026-06-24T16:30Z
EPSS history
Timeline
  • 24 JUN 16:30Z
    drm/msm/dpu: fix mismatch between power and frequency
    cvelistv5