CVE-2026-45945CWE-362

CVE-2026-45945

High · published May 27, 2026

CVSS v3.1
8.8
EPSS
0%
Percentile
2.6
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

iommu/vt-d: Fix race condition during PASID entry replacement

The Intel VT-d PASID table entry is 512 bits (64 bytes). When replacing

an active PASID entry (e.g., during domain replacement), the current

implementation calculates a new entry on the stack and copies it to the

table using a single structure assignment.

struct pasid_entry *pte, new_pte;

pte = intel_pasid_get_entry(dev, pasid);

pasid_pte_config_first_level(iommu, &new_pte, ...);

*pte = new_pte;

Because the hardware may fetch the 512-bit PASID entry in multiple

128-bit chunks, updating the entire entry while it is active (Present

bit set) risks a "torn" read. In this scenario, the IOMMU hardware

could observe an inconsistent state — partially new data and partially

old data — leading to unpredictable behavior or spurious faults.

Fix this by removing the unsafe "replace" helpers and following the

"clear-then-update" flow, which ensures the Present bit is cleared and

the required invalidation handshake is completed before the new

configuration is applied.

The record
Technical detail
CVSS v3.1
8.8 · HIGH
Vector
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H
CVSS v4.0
Not supplied
EPSS
0.00134 · 2.6th percentile
Weakness
CWE-362 · Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')
Published
2026-05-27T18:17Z
Affected products (1)
ProductVersionsFixed in
linux/linux_kernel≥ 6.13, < 6.19.46.19.4
References (3)
EPSS history
Timeline
  • 27 MAY 12:18Z
    iommu/vt-d: Fix race condition during PASID entry replacement
    cvelistv5