CVE-2025-38055

perf/x86/intel: Fix segfault with PEBS-via-PT with sample_freq

published June 18, 2025

CVSS
—
EPSS
0%
Percentile
8.3
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

perf/x86/intel: Fix segfault with PEBS-via-PT with sample_freq

Currently, using PEBS-via-PT with a sample frequency instead of a sample

period, causes a segfault. For example:

BUG: kernel NULL pointer dereference, address: 0000000000000195

<NMI>

? __die_body.cold+0x19/0x27

? page_fault_oops+0xca/0x290

? exc_page_fault+0x7e/0x1b0

? asm_exc_page_fault+0x26/0x30

? intel_pmu_pebs_event_update_no_drain+0x40/0x60

? intel_pmu_pebs_event_update_no_drain+0x32/0x60

intel_pmu_drain_pebs_icl+0x333/0x350

handle_pmi_common+0x272/0x3c0

intel_pmu_handle_irq+0x10a/0x2e0

perf_event_nmi_handler+0x2a/0x50

That happens because intel_pmu_pebs_event_update_no_drain() assumes all the

pebs_enabled bits represent counter indexes, which is not always the case.

In this particular case, bits 60 and 61 are set for PEBS-via-PT purposes.

The behaviour of PEBS-via-PT with sample frequency is questionable because

although a PMI is generated (PEBS_PMI_AFTER_EACH_RECORD), the period is not

adjusted anyway.

Putting that aside, fix intel_pmu_pebs_event_update_no_drain() by passing

the mask of counter bits instead of 'size'. Note, prior to the Fixes

commit, 'size' would be limited to the maximum counter index, so the issue

was not hit.

The record
Technical detail
CVSS
Not scored
CVSS v4.0
Not supplied
EPSS
0.00191 · 8.3th percentile
Published
2025-06-18T09:33Z
EPSS history
Timeline
  • 18 JUN 09:33Z
    perf/x86/intel: Fix segfault with PEBS-via-PT with sample_freq
    cvelistv5