CVE-2025-0647CWE-226

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the…

High · published January 14, 2026

CVSS v3.1
7.9
EPSS
0%
Percentile
5.8
In the wild
Unconfirmed
What it is

⚡ A pesky bug in Arm CPUs could leave your system with outdated memory entries! When executed, a CPP RCTX instruction might ignore critical TLB invalidation, leading to stale information. 🛠️ Think of this like a busy restaurant where the servers forget to clear out old orders from the kitchen. If a new dish is prepared but the old one is still on the table, patrons might end up with a meal they didn't request! This could allow your system to operate with incorrect data, leading to erratic performance or even system crashes. An attacker could take advantage of this oversight to manipulate processes relying on outdated information, potentially compromising system integrity. The ramifications can be quite serious if left unchecked!

Put simply

Think of this like a busy restaurant where the servers forget to clear out old orders from the kitchen. If a new dish is prepared but the old one is still on the table, patrons might end up with a meal they didn't request! In certain Arm CPUs, executing a CPP RCTX instruction can prevent the Translation Lookaside Buffer (TLB) from being invalidated correctly when a TLBI is issued, resulting in stale entries persisting.

What to do

This could allow your system to operate with incorrect data, leading to erratic performance or even system crashes. An attacker could take advantage of this oversight to manipulate processes relying on outdated information, potentially compromising system integrity. The ramifications can be quite serious if left unchecked! To mitigate this, ensure that your system firmware is updated to the latest version addressing this issue. Consult Arm's advisory for specific patches and implement them as soon as possible to maintain optimal performance. You've got this! With the right steps, you can secure your systems and keep everything running smoothly. 🛡️

The record
Technical detail
CVSS v3.1
7.9 · HIGH
Vector
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
CVSS v4.0
Not supplied
EPSS
0.00168 · 5.8th percentile
Weakness
CWE-226 · Sensitive Information in Resource Not Removed Before Reuse
Published
2026-01-14T10:58Z
EPSS history
Timeline
  • 14 JAN 10:58Z
    In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the…
    cvelistv5