CVE-2024-42279

In the Linux kernel, the following vulnerability has been resolved:

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

While transmitting with rx_len == 0, the RX FIFO is not going to be

emptied in the interrupt handler. A subsequent transfer could then

read crap from the previous transfer out of the RX FIFO into the

start RX buffer. The core provides a register that will empty the RX and

TX FIFOs, so do that before each transfer.