CVE-2024-24853CWE-696
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to…
High · published August 14, 2024
What it is
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
The record
Technical detail
- CVSS v4.0
- 7.3 · HIGH
- Vector
- CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H
- EPSS
- 0.00232 · 13.3th percentile
- Weakness
- CWE-696 · Incorrect Behavior Order
- Published
- 2024-08-14T13:45Z
EPSS history
Timeline