CVE-2023-52993

x86/i8259: Mark legacy PIC interrupts with IRQ_LEVEL

Medium · published March 27, 2025

CVSS v3.1
5.5
EPSS
0%
Percentile
18.1
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

x86/i8259: Mark legacy PIC interrupts with IRQ_LEVEL

Baoquan reported that after triggering a crash the subsequent crash-kernel

fails to boot about half of the time. It triggers a NULL pointer

dereference in the periodic tick code.

This happens because the legacy timer interrupt (IRQ0) is resent in

software which happens in soft interrupt (tasklet) context. In this context

get_irq_regs() returns NULL which leads to the NULL pointer dereference.

The reason for the resend is a spurious APIC interrupt on the IRQ0 vector

which is captured and leads to a resend when the legacy timer interrupt is

enabled. This is wrong because the legacy PIC interrupts are level

triggered and therefore should never be resent in software, but nothing

ever sets the IRQ_LEVEL flag on those interrupts, so the core code does not

know about their trigger type.

Ensure that IRQ_LEVEL is set when the legacy PCI interrupts are set up.

The record
Technical detail
CVSS v3.1
5.5 · MEDIUM
Vector
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H
CVSS v4.0
Not supplied
EPSS
0.00269 · 18.1th percentile
Published
2025-03-27T16:43Z
EPSS history
Timeline
  • 27 MAR 16:43Z
    x86/i8259: Mark legacy PIC interrupts with IRQ_LEVEL
    cvelistv5