CVE-2023-5138CWE-1319

Glitch detection not active by default in Silicon Labs Secure Vault High devices

Medium · published January 3, 2024

CVSS v3.1
6.8
EPSS
0%
Percentile
19.3
In the wild
Unconfirmed
What it is

Glitch detection is not enabled by default for the CortexM33 core in Silicon Labs secure vault high parts EFx32xG2xB, except EFR32xG21B.

The record
Technical detail
CVSS v3.1
6.8 · MEDIUM
Vector
CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H
CVSS v4.0
Not supplied
EPSS
0.00273 · 19.3th percentile
Weakness
CWE-1319 · Improper Protection against Electromagnetic Fault Injection (EM-FI)
Published
2024-01-03T22:31Z
EPSS history
Timeline
  • 03 JAN 22:31Z
    Glitch detection not active by default in Silicon Labs Secure Vault High devices
    cvelistv5