CVE-2020-36787

CVE-2020-36787

High · published February 28, 2024

CVSS v3.1
7.8
EPSS
0%
Percentile
13.4
In the wild
Unconfirmed
What it is

In the Linux kernel, the following vulnerability has been resolved:

media: aspeed: fix clock handling logic

Video engine uses eclk and vclk for its clock sources and its reset

control is coupled with eclk so the current clock enabling sequence works

like below.

Enable eclk

De-assert Video Engine reset

10ms delay

Enable vclk

It introduces improper reset on the Video Engine hardware and eventually

the hardware generates unexpected DMA memory transfers that can corrupt

memory region in random and sporadic patterns. This issue is observed

very rarely on some specific AST2500 SoCs but it causes a critical

kernel panic with making a various shape of signature so it's extremely

hard to debug. Moreover, the issue is observed even when the video

engine is not actively used because udevd turns on the video engine

hardware for a short time to make a query in every boot.

To fix this issue, this commit changes the clock handling logic to make

the reset de-assertion triggered after enabling both eclk and vclk. Also,

it adds clk_unprepare call for a case when probe fails.

clk: ast2600: fix reset settings for eclk and vclk

Video engine reset setting should be coupled with eclk to match it

with the setting for previous Aspeed SoCs which is defined in

clk-aspeed.c since all Aspeed SoCs are sharing a single video engine

driver. Also, reset bit 6 is defined as 'Video Engine' reset in

datasheet so it should be de-asserted when eclk is enabled. This

commit fixes the setting.

The record
Technical detail
CVSS v3.1
7.8 · HIGH
Vector
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
CVSS v4.0
Not supplied
EPSS
0.00233 · 13.4th percentile
Published
2024-02-28T14:15Z
Affected products (4)
ProductVersionsFixed in
linux/linux_kernel≥ 5.0, < 5.4.1195.4.119
linux/linux_kernel≥ 5.5, < 5.10.375.10.37
linux/linux_kernel≥ 5.11, < 5.11.215.11.21
linux/linux_kernel≥ 5.12, < 5.12.45.12.4
References (10)
EPSS history
Timeline
  • 28 FEB 08:13Z
    media: aspeed: fix clock handling logic
    cvelistv5