CVE-2020-0574

Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege…

published March 12, 2020

CVSS
—
EPSS
0%
Percentile
29.0
In the wild
Unconfirmed
What it is

Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.

The record
Technical detail
CVSS
Not scored
CVSS v4.0
Not supplied
EPSS
0.00364 · 29.0th percentile
Published
2020-03-12T20:52Z
EPSS history
Timeline
  • 12 MAR 20:52Z
    Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege…
    cvelistv5